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Machine Status Link

Version 1.33 (December 2005) David M. Kline.

The Machine Status Link (MSL) is responsible for distributing the digitized beam current, injection status, P0 clock, and other statuses over a single fiber to several locations around the Storage Ring. The MRD100 is a VME-based module that is part of the MSL and was specifically designed for the APS. It receives and interprets information from the XMS100 module by means of copper or fiber. Signals from the XMS100 module are sent at a P0 rate (3.667 microseconds). It sends two registers every cycle and all in about 12 cycles. Refer to the ASD website for additional information regarding the MSL. The focus of this page is to provide information of how to configure the MRD100 for a beamline IOC and to discuss the sample IOC application.

Hardware Configuration

The MRD100 is configured using both jumpers and switches. The default address is 0xA0000200 and the default IRQ level is IRQ5. The IRQ level can be changed using jumpers J2 and J3 as shown below.

IRQ    J3              J2
1      Jumper IRQ1     Jumper middle two and bottom two pins.
2      Jumper IRQ2     Jumper top two and bottom two pins.
3      Jumper IRQ3     Jumper bottom two pins.
4      Jumper IRQ4     Jumper top two and middle two pins.
5      Jumper IRQ5     Jumper middle two pins.
6      Jumper IRQ6     Jumper top two pins.
7      Jumper IRQ7     No jumpers.

The address can be changed using switches S1, S2, and S3. Each switch represents a byte in the address execept for the LSB that is preset to zero. The switch ON position is set to 0 and OFF is 1. For example, all the switches for the address 0xA0000200 are in the ON position except for SW01, SW21, and SW23.

Switch Switch          Byte
Bank   Number          Number
                       0    LSB
S1     SW00..SW07      1
S2     SW08..SW15      2
S3     SW16..SW23      3    MSB

Most of the registers in the MRD100 are 26 bits wide. Generally, the analog signals are positioned in the lower 16 bits, however some are postioned in the lower 18 bits. The upper bits are typically used for gain and status (i.e. validity). The register contents for canted insertion devices can be viewed here and for non-canted here.

Sample IOC Application

The sample application for the MRD100 contains all the necessary files to build, configure, and run an IOC. It has been built and validated with EPICS base R3.14.6 and R3.14.7. Included are .db and .adl files to provide record instances and sample MEDM displays for the MSL.

The database (.db) files require macro substitution to specify the VME configuration for the INP and OUT fields. The "$(C)" represents the card number, but must be always set to zero (for backward compatibility with the older driver). "$(ID1)" and "$(ID2)" are the prefix IDs for the sector. For example, values of ID1=01 and ID2=01us are used for sector 1. Both fields have the format "#$(C) Sr @s,w,t", where "r" specifies the register number, "@s" indicates the start bit number of the register, "w" indicates the bit width, and "t" is for the data type which can be either 0 for normal or 1 for two's complement signal. Refer to the database files for specific information and usage.

Furthermore, the database is configured to update at a 10 hertz rate. Bit number 24 is the validity bit and is used to trigger the Severity for the data. Additionally, there is a subroutine record to average the xbpm data. The MEDM .adl files require substitution as well for the "$(xx)" and "$(ID1)" macros.

To use the sample application, first download the archive mslApp_R1-33.tar.gz, then refer to README.1ST for further instructions.

Please contact the AOD BCDA group if you need any more information.

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JFM, 11 May 2017
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