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Bunch Clock Generator

Version 1.20 (January 2005) David M. Kline.

The Bunch Clock Generator (BCG) was developed to provide bunch pattern and timing information as an mechanism for triggering beamline instrumentation. The BCG100 is a VME-based A16 module that was designed specifically for a timed resolved experiment in the APS SRI-CAT. The BCG100 receives the P0 revolution clock and a RF 352Mhz signal from another VME-based module referred to as the FRX352. It receives the P0 clock and a 44Mhz signal over fiber and can propagate them to multiple BCG100 modules if required. Furthermore, it converts the 44Mhz signal to the 352Mhz signal for the BCG100. Refer to this document for additional information regarding the Bunch Clock Generator. The focus of this page is to provide information of how to configure the BCG100 for a beamline IOC and to discuss the sample IOC application.

Hardware Configuration

The BCG100 address is configured by using switch bank S2 located towards the back of the module. The address can be changed using switches SW0 through SW9. Each switch represents a bit in the address execept for the lower two bits of the LSB that are preset to zero. The switch ON position is set to 1 and OFF is 0. For example, all the switches for the address 0x7000 are in the 0 position except for SW6, SW7, and SW8. It can be changed by setting the switches as shown below.

    Bit                   Byte
    Number                Number
    3    2    1    0
    0    0    0    0      0    LSB
    SW1  SW0  0    0      1
    SW5  SW4  SW3  SW2    2
    SW9  SW8  SW7  SW6    3    MSB

Furthermore, the IOC example application has been configured with this address (0x700); however, the BCG100 must reside at an address that does not conflict with another A16 VME-based module.

The BCG100 consists of 5 registers, for control / status, RAM address, RAM data, fine delay, and P0 / coarse delay. Refer to this document for additional information. The sample IOC application provides EPICS process variables for accessing these registers.

Sample IOC Application

The sample application for the BCG100 contains all the necessary files to build, configure, and run an IOC. It has been built and validated with EPICS base R3.14.6 and R3.14.7. Included are .db and .adl files to provide record instances and sample MEDM displays for the MSL.

The database (.db) files require macro substitution to specify the process variable prefixes. Specify "$(UNIT)" for "BunchClkGenA.db" and "$(P)" for "BunchClkGen.db" when the databases are loaded in the startup command file (st.cmd). Refer to the database files for specific information and usage. The MEDM .adl files require substitution as well for the "$(UNIT)" macro. Note that typically the macros are subsituted with the sector number.

To use the sample application, first download the archive bcgApp_R1-20.tar.gz, then refer to README.1ST for further instructions.

Please contact the AOD BCDA group if you need any more information.

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JFM, 11 May 2017
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